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s3ci9e0x01 flash interface device samsung electronics 1 s3ci9e0x01 specification version : ver. 1.0 date : jul. 16. 2003 samsung electronics co., ltd semiconductor flash memory product planning & applications
s3ci9e0x01 flash interface device samsung electronics 2 revision history revision no. history draft date remark 0.0 initial draft jan. 24 th 2002 preliminary 0.1 1.on page 18, bsc is moved from bufferram write protection command register to system configuration register and bufferram write protection command register is removed. 2. host interface & nand flash interface (page 3) : 1.8v --> 1.8v / 2.5v / 3.0v jan. 25 th 2002 preliminary 0.2 1. package information is added. 2. some description is updated. 3. controller id register default value is modified. (page 14) 4. write protection nand flash commands are changed, and description are updated.(page 23, 56) mar. 13 th 2002 preliminary 0.3 1. package pin configuration is changed.(page9) 2. software algorithm of detecting nand flash type is added. (page 18, 58) - ce2ena : 11 bit of system configuration register is changed from ?reserved? to ?ce2ena?. apr. 15 th 2002 preliminary 0.4 1. minimum latency at sync. read is changed from 2clocks to 3clocks 2. technical notes are added - write protection truth table is updated(page 58) - write protection guidance is updated(page 58) - internal register reset case is updated(page 61) - pin connection guidance between host and eagle (page 61) - asynchronous page read guidance (page 62) 3. dc/ac parameter is updated(page64~66) : 1 st release parameter 4. tasc parameter is removed. taes parameter is added jun. 21 th 2002 preliminary
s3ci9e0x01 flash interface device samsung electronics 3 4. package dimension information is updated (page63~64) 5. some descriptions are modified & added 0.5 1. vcc is available on 1.8v and 2.5v part. 2. pin j2 is changed from nc to dnu. 3. fig30(state diagram of nand flash write protection) is updated.(page 57 ) 4. internal register reset case table is updated (page 63) 5. dc parameter is updated for 2.5v part (page 66~67) 6. erratas and walk-around methods added (page 73~76) 7. default value of interrupt status register(1442h) is changed from 0000h to 8000h, which is not the silicon revision but definition change.(refer to internal regitster reset case table) (page 22) 9. controller id register value is updated from 1002h to 1202h (page 15) 10. ac parameters are updated (page 65~66) tces, tiacc are added in sync. read. tvlwl is removed in async. write. tava is removed. tcs is added in async. write. dec. 11 th 2002 preliminary 1.0 spec. is finalized jul. 16 th 2003
s3ci9e0x01 flash interface device samsung electronics 4 1. features ! ! ! ! architecture ? design technology : 0.25 m ? voltage supply - main : 1.8v(1.65v~1.95v) / 2.5v(2.3v~2.7v) - host interface & nand flash interface : 1.8v(1.65v~1.95v) / 2.5v(2.3v~2.7v) ? organization - host interface : 16-bit - nand flash interface : 8-bit - little endian addressing ? internal bufferram(4k bytes) - bootram at booting, cache-like at normal operation ? integrated ring oscillator providing clock for nand flash operations ? voltage detector generating internal reset signal from vcc ! ! ! ! performance ? host interface type - synchronous random read : clock frequency : up to 40mhz @30pf - synchronous burst read : clock frequency : up to 40mhz @30pf : burst length : 4words/ 8 words/ 16 words/ 32 words/ continuous linear burst(up to 2k words) - asynchronous random read - asynchronous page read : 4words - asynchronous random write ? programmable read latency ? serial page read - read serial pages by page count register(up to 8 times) ? normal ecc mode / bypass ecc mode is supportable - read operation case :read with ecc - hidden ecc code generation and comparison and 1bit correction :read without ecc - hidden ecc code generation and comparison and readable of ecc result - program operation case :program with ecc - hidden ecc code generation and program it into ecc code
s3ci9e0x01 flash interface device samsung electronics 5 position of nand flash spare :program without ecc ? no operation for ecc ? multiple reset - cold reset / warm reset / hot reset / nand flash reset ? internal bootloader supports booting solution in system ? data protection - write protection mode for bufferram : write protection of buffer ram(first 2pages of buffer ram) - write protection mode for nand flash : block based write protection of nand flash - write protection during power-up ! ! ! ! software ? handshaking feature - int pin : indicates ready/busy of the device - polling method : provides a software method of detecting the ready/busy status of the device ? interface chip id read - detailed chip information by additional controller id register ! ! ! ! packaging ? package - 64ball , 6mm x 6mm x max 1.2mmt fbga ? pin out host interface flash interface power nc, dnu total pin[ea] 35 pins 16 pins 4 pins 9 pins 64 pins
s3ci9e0x01 flash interface device samsung electronics 6 2. general description the device allows standard nand-flash chips to interface with the device bus without performance penalty. this device is 1.8v operation and comprised of about 10,000 gates and 4kb internal bufferram. this 4kb bufferram is used as bootram during cold reset, and is used as cache ram after cold reset. the operating clock frequency is up to 40mhz. this device is x16 interface with host and x8 interface with nand flash. (notice, in this specification, address is expressed by the byte order) also this device has the speed of 55ns random access time. actually, it is accessible with minimum 3clock latency(host-driven clock for synchronous read), but this device adopts the appropriate wait cycles by programmable read latency. the device interface chip provides the serial page read operation by assigning the number of pages to be read in the page counter register. the device is offered in the single type of package ; 6mmx6mmx max 1.2mmt 64ball fbga.
s3ci9e0x01 flash interface device samsung electronics 7 3. pin description pin name type name and description host interface a11~a0 i address inputs - inputs for addresses during read operation, which are for addressing bufferram & register . int o interrupt notifying host when a command has completed. cmos type driver output. dq15~dq0 i/o data inputs/outputs - inputs data during program and commands during all operations, outputs data during memory array/register read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. clk i clock clk synchronizes the device to the system bus frequency in synchronous read mode. the first rising edge of clk in conjunction with navd low latches address input. nwe i write enable nwe controls writes to the bufferram and registers. datas are latched on the nwe pulse?s rising edge navd i address valid detect indicates valid address presence on address inputs. during asynchronous read operation, all addresses are transparent during navd?s low, and during synchronous read operation, all addresses are latched on clk?s rising edge while navd is held low for one clock cycle. > low : for asynchronous mode, indicates valid address ;for burst mode, causes starting address to be latched on rising edge on clk > high : device ignores address inputs nrp i reset pin when low, nrp resets internal operation of eagle and nand flash. nrp status is don?t care during power-up and bootloading. nce i chip enable nce-low activates internal control logic, and nce-high deselects the device, places it in standby state, and places a/dq in hi-z
s3ci9e0x01 flash interface device samsung electronics 8 noe i output enable noe-low enables the device?s output data buffers during a read cycle. nand flash interface i/o 0~i/o7 i/o flash input/output multiplexed command/address/data bus fnce o flash chip enable fnce output is nand flash selection control. when nand flash is in the busy state, fnce high is ignored, and the device does not return to standby mode. fnre o flash read enable fnre output is the serial data-out control, and when active drives the data onto the nand flash i/o bus fnwe o flash write enable fnwe output controls writes to the nand flash i/o port. commands, address and data are latched on the rising edge of the fnwe signal fcle o flash command latch enable fcle output controls the activating path for commands sent to the command register of nand flash. when active high, commands are latched into the command register of nand flash through the i/o ports on the rising edge of the fnwe signal fale o flash address latch enable fale output controls the activating path for address to the internal address registers of nand flash. addresses are latched on the rising edge of fnwe with fale high fnwp o flash write protect fnwp pin provides inadvertent program/erase protection during power transitions and is automatically controlled by eagle. this pin status is activated to ?low? only during power-up. fr/nb i flash ready/busy fr/nb input indicates the status of the nand flash operation. when low, it indicates that a program, erase or random read operation of nand flash is in process and returns to high state upon completion. it is an open drain output and 100k ? pull-up resister is internally connected. so, it does not float to high-z condition when the chip is deselected or when outputs are disabled
s3ci9e0x01 flash interface device samsung electronics 9 power supply vcc-core power for eagle core this is the power supply for eagle core. vcc-io power for eagle i/o(host interface and nand interface) this is the power supply for eagle i/o which is host interface and also nand interface. vss-core ground for eagle core vss-io ground for eagle i/o(host interface and nand interface) etc dnu. do not use leave it disconnected. these pins are used for testing. nc no connection lead is not internally connected. note : do not leave power supply( vcc, vss) disconnected.
s3ci9e0x01 flash interface device samsung electronics 10 4. pin configuration notice: dnu (c10, g10,j2)pins are used as test pin, so please leave these pins disconnected. dnu pins can be connected with the limitation that they must be low. 64ball fbga eagle chip 6 mm x 6 mm x max 1.2mmt , ball pitch : 0.5 mm (topview, balls facing down) nc i/o6 i/o5 i/o2 vss-io i/o0 fnwe i/o7 nwe nc i/o4 i/o3 i/o1 fcle fnre int nrp noe fnrb nc nc vcc-io 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k vss-core dnu dq15 dq14 vcc-core fnce1 dq13 dq7 a 3 fale dq12 dq8 a 5 fnwp dq10 dq4 a 9 dnu dq9 dq0 a 10 a 2 dq6 dnu dq5 dq2 nce a 7 a 0 dq11 fnce2 a 4 nc dq3 flsclk navd a 11 a 8 a 6 dq1 a 1 nc
s3ci9e0x01 flash interface device samsung electronics 11 5. block diagram for eagle interface chip - - eagle flash interface - 4kb bufferram - command and status registers - state machine ( bootloader is included) - error correction logic - standard nand flash interface note: 1) at cold reset, bootloader copies bootcode(4k byte size) from nand flash to bufferram. and except cold reset host can use bufferram like cacheram. vcccore vsscore bufferram (4k bytes) 1) internal registers (address/command/configuration /status registers) state machine error correction logic standard nand flash interface eagle flash interface nwe nce cl k noe nrp fcle navd fale fnce2 fnre fnwp fr/nb i/o0~i/o7 dq0~dq15 bootloader fnwe a0~a11 int vccio fnce1 vssio
s3ci9e0x01 flash interface device samsung electronics 12 6. address map for eagle interface chip notice ) address expression in this specification was used byte order for customer?s convenience. word order value can be calculated by 1bit-right shift of byte order value. address (byte order) size (total 8kb) usage description 0000h ~ 01feh 512b pb0 main area buffer 0 0200h ~ 03feh 512b pb1 main area buffer 1 0400h ~ 05feh 512b pb2 main area buffer 2 0600h ~ 07feh 512b pb3 main area buffer 3 0800h ~ 09feh 512b pb4 main area buffer 4 0a00h ~ 0bfeh 512b pb5 main area buffer 5 0c00h ~ 0dfeh 512b pb6 main area buffer 6 0e00h ~ 0ffeh 512b 4kb pb7 main area buffer 7 1000h ~ 100eh 16b sb0 spare area buffer 0 1010h ~ 101eh 16b sb1 spare area buffer 1 1020h ~ 102eh 16b sb2 spare area buffer 2 1030h ~ 103eh 16b sb3 spare area buffer 3 1040h ~ 104eh 16b sb4 spare area buffer 4 1050h ~ 105eh 16b sb5 spare area buffer 5 1060h ~ 106eh 16b sb6 spare area buffer 6 1070h ~ 107eh 16b 128b sb7 spare area buffer 7 1080h ~ 13feh 896b 896b reserved - 1400h ~ 17feh 1kb 1kb registers internal registers 1800h ~ 1ffeh 2kb 2kb reserved - note : - data output is 00h while host reads/writes from/to a register bit of reserved area.
s3ci9e0x01 flash interface device samsung electronics 13 ? spare area buffer - 0x1000 ~ 0x107e : 8 (page counter) x 16 byte(nand spare area) = 128b address f e d c b a 9 8 7 6 5 4 3 2 1 0 1000h(sb0) lsn(2 nd ) lsn(1 st ) 1002h(sb0) wc(1 st ) lsn(3 rd ) 1004h(sb0) bi wc(2 nd ) 1006h(sb0) ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 1008h(sb0) ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 100ah(sb0) reserved ecc code for spare area data (2 nd ) 100ch(sb0) reserved reserved 100eh(sb0) reserved reserved 1010h~ 101eh(sb1) 1020h~ 102eh(sb2) 1030h~ 103eh(sb3) 1040h~ 104eh(sb4) 1050h~ 105eh(sb5) 1060h~ 106eh(sb6) 1070h~ 107eh(sb7) sb1 ~ sb7 have same assignment like sb0. note: - lsn : logical sector number - wc : wrap count and each byte has same wrap count information and these are used as error correction for wrap count itself. - bi : bad block information > host can use complete spare area except bi and ecc code area. for example, host can write data to ?reserved area of spare area buffer? at program operation. > eagle automatically generates ecc code for both main and spare data during eagle?s data loading to nand flash, but does not update ecc code to spare buffer. > when programming/reading spare area, spare area buffer number(sb0~7) is chosen via start buffer register as it is. equivalent to 1byte of nand flash equivalent to 1byte of nand flash
s3ci9e0x01 flash interface device samsung electronics 14 7.internal registers for eagle interface chip address (byte order) name host access description 1400h controller information r detailed information including device id is offered 1402h block address r/w block address of the flash memory 1404h page address & page count r/w 8-bit msb: the page address in a block 8-bit lsb: the page count which represents the number of pages to be accessed 1406h start buffer r/w specifies the buffer number for the page data transfer to/from the flash memory 1408h ~ 141eh reserved - 1420h command r/w host control commands and flash memory operation commands 1422h system configuration r/w flash configuration and host interface configuration 1424h ~143eh reserved - 1440h controller status r controller status and the result of flash operation 1442h interrupt r/w flash command completion interrupt status 1444h reserved - 1446h ecc result of main area data r ecc error position of main area data error 1448h ecc result of spare area data r ecc error position of spare area data error 144ah nand flash write protection command r/w nand flash write protection command to make nand flash be secured 144ch unlock start block address r/w start nand flash block address to unlock in write protection mode 144eh unlock end block address r/w end nand flash block address to unlock in write protection mode 1450h nand flash r current nand flash write protection status whether
s3ci9e0x01 flash interface device samsung electronics 15 write protection status unlocked /locked /lock-tighten 1452h~17feh reserved - note : - data output is 00h while host reads/writes from/to a register bit of reserved area. 7.1. address register 7.1.1. controller id register (r) : 1400h, default = 1202h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 manucode vercode chipid bufsize manucode (manufacturer code): manufacturer identification, 1h for samsung electronics corp. vercode (version code): the version of the chip, which is updated like the following cases. - process change (even if no change in logical interface) - dc/ac parameter change - error correction of existing silicon. version controller id reigister value 1.0 1002h 1.1 / 1.2 1202h chipid (chip id): the id of the chip, which is updated like the following cases. - device change - changes requiring some sw-change or some completely new silicon. bufsize (buffer size): the size of internal page buffer. bufsize page buffer size in kbytes 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 (default) 0 0 1 1 6 0 1 0 0 8 0101~ 1111 reserved
s3ci9e0x01 flash interface device samsung electronics 16 7.1.2. block address register (r/w): 1402h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ba ba (block address): nand flash block address which will be read or programmed or erased.. nand flash valid bits 64mb ba[8:0] 128mb ba[9:0] 256mb ba[10:0] 512mb ba[11:0] 1gb ddp ba[12:0] 7.1.3. address length register : page address & page counter register (r/w): 1404h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pa reserved pc pa (page address): nand flash start page address in a block for page read or program operation. pa(default value) = 00000 pa range : 00000 ~ 11111 pc (page count): this field specifies the number of pages to be read. its maximum count is 8 pages at 000(default value) value. for a single page access, it should be programmed as value 001. however internal ram buffer reached to 111vaule(max value), it counts up to 000value to satisfy pc value. for example) if sb = 110 , pc = 100 then selected bufferram are ? 110 ! 111 ! 000 ! 001 ? 7.1.4. start buffer register (r/w): 1406h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sb sb (start buffer) : it is the place where data is placed and specifies the start buffer number(0~7 th ) in the internal bufferram(0~7 th ) (see address map).
s3ci9e0x01 flash interface device samsung electronics 17 7.2. command and system configuration registers 7.2.1. command register (r/w): 1420h, default = 0000h 15 14 13 12 11 10 9 8 * 7 6 5 4 3 2 1 0 reserved cmd * 9 th bit of cmd determines whether ecc generation or ecc generation bypass. 9 th bit value: ?0? ? ecc generation , ?1? ? bypass ecc generation and ecc generation is available on read/program operation. the cmd field specifies the operation that the controller will perform. cmd operation acceptable command during busy 0000h (0 0000 0000) read single page 1) of flash with ecc correction f0h , f3h 0100h (1 0000 0000) read single page 1) of flash without ecc correction f0h , f3h 0003h (0 0000 0011) read single spare area of flash with ecc correction f0h , f3h 0103h (1 0000 0011) read single spare area of flash without ecc correction f0h , f3h 0085h (0 1000 0101) program single page 1) of flash with ecc generation f0h , f3h 0185h (1 1000 0101) program single page 1) of flash without ecc generation f0h , f3h 008ah (0 1000 1010) program single spare area 1) of flash with ecc generation f0h , f3h 018ah (1 1000 1010) program single spare area of flash without ecc generation f0h , f3h 0094h (0 1001 0100) erase single block of flash f0h , f3h 000ch (0 0000 1100) read flash memory id f0h , f3h 00f0h (0 1111 0000) reset flash memory - 00f3h (0 1111 0011) reset controller 2) - note : 1) ?page? means all(528b) of main area(512b) and spare area(16b) in nand flash.
s3ci9e0x01 flash interface device samsung electronics 18 host can read/program by page(main+spare area) unit or by spare area unit. at read/program by page unit, sb(start buffer) of spare area is same to that of main area. 2) ?reset controller?(=hot reset) command makes the registers default state as the warm reset(=reset by nrp pin). > serial pages read can be performed by setting the pc (page counter). : pc(default) = ?0? (8 pages) : pc value is available up to 8. " " " " command input guide 1. once previous command is entered, followed next command input cause erroneous operation. to cancel previous command, resets(nrp ,f3h, f0h) are recommended. 2. during int is low, only resets(nrp, f3h,f0h) are acceptable. 3. please avoid another resets input during one reset operation. previous command next command previous command reset ( nrp,f3h,f0h ) command command int int return time by reset is max. 5us(at read) / 50us(at program) /500us(at erase). reset ( nrp,f3h,f0h )
s3ci9e0x01 flash interface device samsung electronics 19 7.2.2. system configuration register (r/w): 1422h, default = 7051h > system configuration register is not adjusted automatically to nand flash device type(density , version). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rm brl ce2ena bl ps bs fbw bss rm (read mode): this field specifies the selection between asynchronous read mode and synchronous read mode brl (burst read latency): this field specifies the initial access latency in the burst read transfer. in 40mhz, 011(3-cycle) is proper value. ce2ena (nand flash type): this field specifies nand flash type whether 512mb single or 512mb ddp. rm read mode 0 asynchronous read (default) 1 synchronous read brl latency cycles 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3-cycle (min.) 1 0 0 4-cycle 1 0 1 5-cycle 1 1 0 6-cycle 1 1 1 7-cycle (default) ce2ena nand flash type 0 512mb single nand flash (default) 1 256mb x 2ea with dual nce nand flash
s3ci9e0x01 flash interface device samsung electronics 20 bl (burst length): this field specifies the size of burst length during sync. burst read. ps (page size): this field specifies the size of a page in the flash memory. ps page size in bytes 0 0 reserved 0 1 512 (default) 1 0 reserved 1 1 reserved bs (block size): this field specifies the size of a block in the flash memory. bs block size in kbytes 0 0 8 0 1 16 (default) 1 0 reserved 1 1 reserved fbw (flash bus width): this field specifies the bus width of the flash memory bus. fbw bus width in bits 0 0 8 (default) 0 1 reserved 1 0 reserved 1 1 reserved bss (buffer write protection set): this field specifies the buffer write protection status of first 2page buffer. bl burst length 0 0 0 continuous (default) 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 0 0 32 words 1 0 1~1 1 1 reserved
s3ci9e0x01 flash interface device samsung electronics 21 bss buffer write protection set 0 0 locked 0 1 locked (default) 1 0 unlocked 1 1 locked 7.3. status registers 7.3.1. controller status register (r): 1440h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cb reserved pr erm ers reserved cb (controller busy): this bit shows the overall internal status of the controller. set to ?1? when the controller is in its operation and cannot receive any more command. ?0? when the controller is in ready state. cb controller busy status 0 ready 1 busy pr (program result): this bit shows the result of page program/block erase operation for flash memory. pr program/erase result 0 successful 1 error in program/erase erm (ecc error for main area data) & ers (ecc error for spare area data) : erm and ers show the number of error in a page as a result of ecc check at the page read operation. : ecc algorithm of eagle can?t detect and correct above 2 fault bits per page, interprets that case as uncorrectable. erm, ers ecc status 0 0 no error
s3ci9e0x01 flash interface device samsung electronics 22 0 1 1-bit error(correctable) 1 0 2 bits error (uncorrectable) 1) 1 1 2bits error at serial-pages read(uncorrectable) 2) note: 1) 3bits or more error detection is not supported 2) at serial-pages read by the number of pc, erm and ers represent cumulative result of those pages. for example, if there are 2pages with 2bits error in main/spare area data, erm/ers value is 11. if there are 2pages with 1bit error in main/spare area data, erm/ers value is 01. to find where error is, host must check each of serial pages. 7.3.2. interrupt status register (r/w): 1442h, default = 8000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 int reserved ri wi ei idi reserved bit address bit name default state valid states function 0 interrupt off 15 int (interrupt) : the master interrupt bit -set to '1' of itself when one or more of ri,wi,ei,idi is set to ?1? ,or boot is done, or warm reset is released , or hot reset is released. -cleared to '0? when by writing ?0? to this bit or by reset(cold/warm/hot reset). ?0? in this bit means that int pin is low status. (this int bit is directly wired to the int pin on the chip, so the pin will go low upon writing ?0? to this bit) 0 1 interrupt pending 7 ri (read interrupt): 0 0 interrupt off
s3ci9e0x01 flash interface device samsung electronics 23 -set to '1' of itself at the completion of read operation -cleared to '0? when by writing ?0? to this bit or by reset(cold/warm/hot reset). 1 interrupt pending 0 interrupt off 6 wi (write interrupt): -set to '1' of itself at the completion of program operation -cleared to '0? when by writing ?0? to this bit or by reset(cold/warm/hot reset). 0 1 interrupt pending 0 interrupt off 5 ei (erase interrupt): -set to '1' of itself at the completion of erase operation -cleared to '0? when by writing ?0? to this bit or by reset(cold/warm/hot reset). 0 1 interrupt pending 0 interrupt off 4 idi (id interrupt): -set to '1' of itself at the completion of read id operation -cleared to '0? when by writing ?0? to this bit or by reset(cold/warm/hot reset). 0 1 interrupt pending 7.3.3. ecc result of main area data register (r) : 1446h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ecc result 1 1) ecc result2 2) 7.3.4. ecc result of spare area data register (r) : 1448h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ecc result3 3) ecc result 2 2) note) 1. ecc result 1 : ecc error position address that selects one of main area data (512bytes). 2. ecc result 2 : ecc error position address which selects one of eight i/os (i/o 0~i/o7). 3. ecc result 3 : ecc error position address that selects one of logical sector
s3ci9e0x01 flash interface device samsung electronics 24 number (3bytes) * at serial-page read operation, these ecc result registers have result for last page. 7.3.5. nand flash write protection command (r/w) : 144ah, default = 0002h 15 14 13 12 11 10 9 8 * 7 6 5 4 3 2 1 0 reserved write protection command* note : *the cmd field specifies the operation which the controller will perform. nand flash write protection command operation 0004h ( 0000 0100) unlock nand flash block(s) according to given block address range 0002h ( 0000 0010) lock all nand flash block(s) 0001h ( 0000 0001) lock-tight locked block(s) 7.3.6. unlock start block address (r/w) : 144ch, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved usba usba (unlock start block address): start nand flash block address to unlock in write protection mode, which follows ?unlock block command?. 7.3.7. unlock end block address (r/w) : 144eh, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ueba ueba (unlock end block address): end nand flash block address to unlock in write protection mode, which follows ?unlock block command?. 7.3.8. nand flash write protection status (r) : 1450h, default = 0002h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved us ls lts
s3ci9e0x01 flash interface device samsung electronics 25 us (unlocked status): ?1? value of this bit specifies that there is unlocked block in nand flash. ls (locked status): ?1? value of this bit specifies that all nand flash blocks are in locked status. lts (lock-tighten status): ?1? value of this bit specifies that ?locked block(s)? is lock-tighten. > while anyone of these three bits(us,ls,lts) is set, the others are internally reset 8. access timings for eagle interface chip operation nce noe nwe a0~15 dq 0~15 nrp flsclk navd standby h x x x high-z h x x warm reset x x x x high-z l x x asynchronous write l h l add. in data in h x asynchronous read l l h add. in data out h l or load initial burst address l h or l h add in x h or burst read l l h x burst dout h or terminate burst read cycle h x h x high-z h x x terminate burst read cycle via nrp x x x x high-z l x x terminate current burst read cycle and start new burst read cycle h h add in high-z h < bus operation > x=don?t care
s3ci9e0x01 flash interface device samsung electronics 26 8.1. asynchronous read operation host nand flash eagle page write block erase page read < access types > figure 1. asynchronous read mode async. write async. random read sync. read async. page read nwe clk nrp noe tce nce ai toe tacc dqi v alid data toh valid address taes* * please notice, taes is address delay from nce & navd?s low, and taes should not be over 10ns. tae
s3ci9e0x01 flash interface device samsung electronics 27 8.2. latched asynchronous read operation figure 2. latched asynchronous read mode nwe clk nrp noe tce nce navd ai toe tacc dqi v alid data toh tasa valid address taes* tae
s3ci9e0x01 flash interface device samsung electronics 28 8.3. asynchronous page read operation figure 3. asynchronous page read mode nwe clk noe nrp nce tce navd valid address tacc dqi data0 data1 data2 data3 v a lid address v a lid address ?l? toh toe tapa tasa a 11~2 valid address a 1~0 v a lid address taes* tae * please notice, taes is address delay from nce & navd?s low, and taes should not be over 10ns.
s3ci9e0x01 flash interface device samsung electronics 29 8.4. synchronous burst read operation figure 4. synchronous burst read mode tbacc tbdh tiacc tavds tacs tach nwe clk noe nrp nce tces navd int ai valid address read latency : 7clock(default), 3clock(min.) toh toh dqi data data data tavdh
s3ci9e0x01 flash interface device samsung electronics 30 8.5. asynchronous write operation (no navd pin case) figure 5. asynchronous write mode int nwe noe nrp nwp nce clk twpl twph twc tcs tch tds tdh ai valid address dqi valid data valid address valid data
s3ci9e0x01 flash interface device samsung electronics 31 8.6. latched asynchronous write operation 9. timing diagram for eagle interface chip figure 6. latched asynchronous write mode int nwe noe nrp nwp nce navd clk twpl tavdp twph twc tcs tch tds tdh ai valid address taavds taavdh dqi valid data valid address valid data
s3ci9e0x01 flash interface device samsung electronics 32 9.1. asynchronous read operation the read cycle is initiated by first applying address to the address bus. the address latch is transparent while nce is low. the random access time is measured from a stable address, falling edge of nce. the clock should remain ?0? during asynchronous access. address access time(tacc) is equal to the delay from stable addresses to valid output data. the chip enable access time(tce) is the delay from the stable addresses and stable nce to valid data at the outputs. the output enable access time(toe) is the delay from the falling edge of noe to valid data at the output. nce must toggle in asynchronous read operation. figure 6. asynchronous read mode tacc noe toe nce tce ai valid address dqi valid data taes tae
s3ci9e0x01 flash interface device samsung electronics 33 9.2. lathced asynchronous read operation the read cycle is initiated by first applying address to the address bus. the address latch is transparent while navd is low. the random access time is measured from a stable address, falling edge of navd or falling edge of nce which ever occurs last. the clock should remain ?0? during asynchronous access. address access time(tacc) is equal to the delay from stable addresses to valid output data. the chip enable access time(tce) is the delay from the stable addresses and stable nce to valid data at the outputs. the output enable access time(toe) is the delay from the falling edge of noe to valid data at the output. nce and navd must toggle in asynchronous read operation. 9.3. asynchronous page read operation asynchronous page read mode is the default state and provides a high data transfer rate for non clocked memory subsystems. the page size is four words, and a 1~0 addresses one of the four words. the read cycle is initiated by first applying address to the address bus. the address latch is transparent while navd is low. the address is latched by internal address latch circuit. the random access time is measured from a stable address, falling edge of navd figure 7. asynchronous read mode navd tacc noe toe nce tce ai valid address dqi valid data taes tae
s3ci9e0x01 flash interface device samsung electronics 34 or falling edge of nce which ever occurs last. the clock should remain ?1? during asynchronous access. address access time(tacc) is equal to the delay from stable addresses to valid output data. the chip enable access time(tce) is the delay from the stable addresses and stable nce to valid data at the outputs. the output enable access time(toe) is the delay from the falling edge of noe to valid data at the output. nce and navd must toggle in asynchronous read operation. figure 8. asynchronous page read mode navd nce noe clk tacc dqi data0 data1 data 3 ?l? data2 valid address v a lid address v a lid address v a lid address toh tasa tce tae toe tapa a 11~2 a 1~0 valid address taes
s3ci9e0x01 flash interface device samsung electronics 35 9.4. synchronous burst read operation when the device is powered up, it defaults to asynchronous read operation. burst mode is selected by system configuration register bit 15. the burst mode is used to improve the data transfer between the memory and the system processor. the burst mode is used only for read operations. burst length is available on 4words/ 8words/ 16words/ 32words/ continuous length, and is set by bl of system configuration register. the bus controller in the system will insert required read latency to meet host random access time. the first access time in the burst is equal to the random access time. in the burst access, the address is latched at the rising edge of the clock pulse when navd is low. the first data in the burst access is available after the random access time. the bus controller reads data at the first rising edge of the clock after read latency. there is no conflict between navd?s low and noe?s low. the output buffers need to settle before the first data is available. due to this, the shortest random access is at least one clock cycles from the rising edge of the clock when navd is low. this is defined as random access without any wait state. as the random access is allowed to be much longer than one clock cycles, the flash device has to support wait state insertion in order to synchronize the start of the burst access. figure 9. synchronous burst read mode( 3clock read latency case) navd nce noe clk ai valid address tiacc tbacc tbdh data0 data1 data3 dqi data2
s3ci9e0x01 flash interface device samsung electronics 36 9.5. programmable read latency the programmable read latency value indicates to the device the number of additional clock cycles that must elapse after navd is driven active before data will be available. the number of read latency that should be programmed into the device is directly related to the clock frequency. upon power up, the device defaults to seven cycles. the total number of the read latency is programmable from zero to seven cycles. a hardware reset will set read latency to seven cycles after power-up. the minimum read latency for this device is three cycle assuming 40mhz system clock. figure 10. example of 3clock read latency insertion data 0 navd noe clk tbacc tiacc 0 1 2 3 number of clock cycles programmed rising edge of the clock cycle following last read latency triggers next burst data tbdh dqi valid address ai data 1 data 2 data 3 data 4
s3ci9e0x01 flash interface device samsung electronics 37 9.6. asynchronous write operation write is allowed only in the asynchronous mode. the address is latched at the rising edge of the nce signal. the random access time is measured from a stable address, falling edge of nce. write operations are asynchronous. therefore, clk is ignored during write operation. there is no conflict between nce?s low and noe?s low. figure 11. asynchronous write mode nwe nce tdh tds valid address ai valid data dqi
s3ci9e0x01 flash interface device samsung electronics 38 9.7. latched asynchronous write operation at latched asynchronous write operation, the address is latched at the rising edge of the navd signal. because write operations are asynchronous operation, clk is ignored during write operation. there is no conflict between navd?s low and noe?s low. figure 12. latched asynchronous write mode nwe nce navd address latch tdh tds valid address ai valid data dqi tch
s3ci9e0x01 flash interface device samsung electronics 39 10. device operation for eagle interface chip 10.1. read controller id the device contains a controller id register, can be read by accessing controller id register(address = 1400h) with synchronous/asynchronous read timing. figure 12 shows the ?read controller id? operation by asynchronous read timing. navd address latch noe nce ai address:1400h figure 13. read controller id (lached asynchronous read case) dqi id data
s3ci9e0x01 flash interface device samsung electronics 40 10.2. read nand flash id ?read nand flash id? mode is initiated by writing 000ch command to 1420h register. before writing command, host must write the start buffer address which nand flash id will be placed. as a result of this operation, nand flash id is stored sequentially in lsb(1 st and 2 nd word) of the start buffer ; the maker code(ech), and the device code (xxh 1) ) , and reserved(2cycle). figure 14. flow chart of ?read nand flash id? operation 1 st word 2 nd word maker code 2) device code 2) reserved reserved start buffer note : 1) device code is different according to product ( 64mb ? 39h, 128mb ? 33h, 256mb ? 35h ) 2) these are little endian addressing wait for int register low to high transition write start buffer address to 1406h register start read nand flash id from start buffer end write command 000ch to 1420h register write ?0? to ?int? bit of 1442h
s3ci9e0x01 flash interface device samsung electronics 41 10.3. reset operation 10.3.1 cold reset (system power-up case, bootcode-loading trigger) at system power-up, eagle detects it and generates internal power-up reset signal which triggers bootcode-loading. bootcode-loading means that bootloader in eagle copies designated-sized data(i.e 4k bytes bootcode) from nand flash to bufferram(4k bytes). bufferram accesses are o.k, even if int is still low after bootloading has happened. reading and writing from/to registers is o.k as long as there is no nand command. 10.3.2 warm reset(by nrp pin) warm reset means that host resets eagle by nrp pin, and then eagle stops all current note: 1) 4k bytes bootcode copy takes 500us(estimated) host must read bootcode in bufferram(4k bytes) after bootcode copy completion. 2) int register goes ?low? to ?high? on the condition of ?bootcode-copy done? and nrp rising edge. if nrp goes ?low? to ?high? before ?bootcode-copy done?, int register goes to ?low? to ?hi g h? as soon as ?bootcode-co py done? system power internal power-up reset signal eagle operation bootcode copy sleep idle por is activated and then ring oscillator is activated nrp 1) bootcode-copy done por triggering level figure 15. cold reset timings int 2)
s3ci9e0x01 flash interface device samsung electronics 42 operation and executes warm reset operation 1) , and eagle resets current nand flash operation. device will not be reset in case of nrp pulses shorter than 50ns, but device is guaranteed to be reset in case nrp pulse is longer than 500ns. warm reset has no effect for contents of main/spare area buffers 10.3.3 hot reset(eagle reset command input case) hot reset means that host resets eagle by reset command, and then eagle stops all current operation and executes hot reset operation 1) , and resets current nand flash operation. hot reset has no effect for contents of main/spare area buffers nrp eagle operation warm reset operation idle idle initiated by nrp low int eagle operation hot reset opreation 1) idle idle navd 00f3h nce nwe dqi figure 16. warm reset timings ai 1420h int
s3ci9e0x01 flash interface device samsung electronics 43 note 1) internal reset operation means that eagle initializes internal registers and makes output signals go to default status. 10.3.4 flash reset(flash reset command input case) host can reset nand flash by flash reset command. figure 17. hot reset timings eagle operation flash reset operation idle idle navd nce nwe flash r/nb figure 18. flash reset timings 00f0h dqi ai 1420h int
s3ci9e0x01 flash interface device samsung electronics 44 10.4. program operation ( programming nand ) eagle has input/outputs that accept both address and data information. when host writes data into a nand flash memory via eagle interface device, firstly, host reads controller id from controller id register. host must drive clk, navd, and nce to ?low? state and noe to ?high? state when providing an address to the device, and drive clk, nwe and nce to ?low? state, and noe to ?high? state when writing commands or data. next, the program address and data are written, which in turn initiate programming nand flash memory. firstly, host writes block address(ba) of nand to ?block address register? and page address(pa) of nand to ?page address register? also writes nand program command to command register in device. interruption signal is enabled only after nand flash memory is programmed according to the nand flash program timings. it takes 220us ~ 550us to execute nand program procedure. when program operation of nand is finished, nand returns status value and the status is written in status register in device. the host detects the status of the program operation by monitoring input/output pins. in spare area buffer, all sixteen bytes which are logical sector number area, wrap count, bad block information, ecc code area, and reserved area are accessible for host. multi-page program operation is not available, only one- page program operation is available.
s3ci9e0x01 flash interface device samsung electronics 45 note 1) refer to command table write register address 1420h write program command 1) wait for int register low to high transition typ. : 200us max. : 550us read controller status register write register address 1440h program error i/o7 = 0 ? program completed yes no write register address 1406h write register address 1404h write register address 1402h write ?ba? of flash data input completed? no start write ?pa? of flash yes write ?sb? write ?0? to int registe r of interrupt register write data write buffer column address
s3ci9e0x01 flash interface device samsung electronics 46 figure 19.flow chart of program operation figure 20. program operation timings note) wa : register address to write nand flash address/command fa : nand flash address(block address) to program ( refer to address register table) cmd : program command ( refer to command register table) sra : status register address ( refer to status register table) nce noe nwe tds tdh tch navd fa cmd dqi program operation twpl twph flash r/nb srd tprog(typ.) = 220us~500us fa 1 word data loading 264 word(=1 page) data loading command register setting status register read address register setting wa ai wa sra wa int twc
s3ci9e0x01 flash interface device samsung electronics 47 10.5. erase operation ( erasing nand ) firstly, same id read operation as programming nand operation is executed and then host must drive clk, navd, and nce to ?low? state and noe to ?high? state when providing an address to the device, and drive clk, nwe and nce to ?low? state, and noe to ?high? state when writing commands. firstly, host writes block address(ba) of nand to ?block address register? and also writes nand erase command in command register in device. interruption signal is enabled only after nand flash memory is erased according to the nand flash erase timings. it takes 2ms ~ 3ms to execute nand erase procedure. when erase operation of nand is finished, nand returns status value and the status is written in status register in device. the host detects the status of erase operation by monitoring input/output pins. fi g ure 21. flow chart of erase o p eration write register address 1420h wait for int register low to high transition typ. : 2ms max. : 3ms read controller status register write register address 1440h erase error i/o7 = 0 ? erase completed yes no write register address 1402h write ?ba? of flash start write ?0? to int registe r of interrupt register write erase command(0094h)
s3ci9e0x01 flash interface device samsung electronics 48 ` figure 22. erase operation timings note) wa : register address to write nand flash address/command fa : nand flash address(block address) to erase ( refer to address register table) cmd : erase command(94h, refer to command register table) sra : status register address ( refer to status register table) navd fa cmd nce noe nwe tds tdh tch erase operation twpl twph flash r/nb srd tbers(typ.) = 2ms~3ms dqi wa wa sra ai int
s3ci9e0x01 flash interface device samsung electronics 49 10.6 . read operation ( reading nand ) read operation is just a transferring data from nand flash memory to interface chip internal registers. inputting command sequence procedure is same as the above write or erase operation in the same condition. firstly, host writes block address, page address and page counter value of nand is assigned in address register in order and also writes nand read command in command register in device. and then initiated nand flash memory is accessed and transferring data from nand flash memory array to the interface chip internal buffers at the assigned address. these data size increases as multiple of 528 bytes, that is, one page size of nand flash memory. interruption signal is enabled only after nand flash memory is read according to the nand flash read timings. it takes typically 35 us to execute nand read procedure while page counter is set to 001 which means one page read. if page counter is set to above 001 which means multi page read, read operation from nand will be executed sequentially as many as assigned in page counter number. when read operation of nand is finished, nand returns status value and the status is written in status register in device. the host detects the status of read operation by monitoring input/output pins. buffer ram is dual port ,therefore host can access page in buffer ram while state machine is accessing another page in buffer ram.
s3ci9e0x01 flash interface device samsung electronics 50 figure 23. flow chart of read operation write register address 1420h write read command 1) wait for int register low to high transition typically ?35us? at single page read operation, and ?35us x pc? at multi-read operation. read controller status register write register address 1440h error exist? read completed yes no write register address 1406h write register address 1404h write register address 1402h write ?ba? of flash start write ?pa? of flash & ?pc? write ?sb? write ?0? to int registe r of interrupt register note 1) refer to command table 1bit error? map out automatically corrected yes no
s3ci9e0x01 flash interface device samsung electronics 51 note) wa : register address to write nand flash address/command fa : nand flash address(block address) to read ( refer to address register table) cmd : read command( refer to command register table) sra : status register address ( refer to status register table) navd nce noe nwe tds tdh tch read operation twpl twph flash r/nb tr(typ.) = 10us figure 24. read operation timings fa srd dqi wa wa sra ai cmd int
s3ci9e0x01 flash interface device samsung electronics 52 10.7. ecc operation 10.7.1 ecc operation case while eagle accesses nand flash for program operation, hiddenly generates ecc code(24bits for main area data and 10bits for lsn of spare area data), and while for read operation, hiddenly generates ecc code and detects error number and position and corrects 1bit error. figure 25 shows ecc code assignment of nand flash spare area, and this ecc code is updated by eagle automatically. after read operation, host can know whether there is error or not by reading ?status register?(refer to controller status register table). error type is divided into ?no error?, ?1bit error(correctable)?, ?above 2bit error(uncorrectable)?. since generated ecc code at read/write operation is not updated to internal buffer ram but is updated to nand flash spare area directly. host can read generated ecc code only from nand flash spare area. 10.7.2 ecc bypass operation case ecc bypass operation is set by 9 th bit of cmd register. in ecc bypss operation, eagle hiddenly generates ecc result which indicates error position(refer to ecc result table), but doesn?t correct. after read operation, host can know whether there is error or not by reading ?status register?(refer to controller status register table). error type is divided into ?no error?, ?1bit error(correctable)?, ?above 2bit error(uncorrectable)?. in 1bit error case, host can correct the error by itself after reading ecc result register. " " " " ecc code / result readability read operation program operation operation ecc code from spare area buffer ecc result from register (1446h,1448h) ecc code from spare area buffer ecc result from register (1446h,1448h) ecc operation invalid (pre-written ecc code 1) ) valid invalid (old data 2) ) - ecc bypass invalid (pre-written ecc code) valid invalid (old data) - note 1) pre-written ecc code : ecc code which is previously written to nand flash spare area in program operation. 2) old data : ecc code is not updated to spare buffer, so ecc code placement of spare buffer remains old data. figure 25. ecc code/result readability
s3ci9e0x01 flash interface device samsung electronics 53 f e d c b a 9 8 7 6 5 4 3 2 1 0 reserved 5) 4) 3) 2) 1) 1) logical sector number (lsn) 2) wrap counter :status flag against sudden power failure during write 3) bad block information 4) ecc code for main area data(24bits) 5) ecc code for spare area data(lsb 10bits) figure 26. nand flash spare area assignment
s3ci9e0x01 flash interface device samsung electronics 54 figure 27. ecc operation guidance " " " " ecc operation guidance 1. ecc generation and correction by eagle : program with ecc operation / read with ecc operation 2. ecc generation by eagle & correction by host : program with ecc operation / read without ecc operation * host can read ecc result from ecc result register after read operation in both ecc operation and ecc bypass case. " " " " ecc operation example 1) when eagle read nand flash main+spare area data without ecc --> eagle place the data read from nand flash spare/ecc locations into the buffer for both main and spare ecc 2) when eagle read nand flash main+spare area data with ecc --> eagle doesn't place the data read from nand flash spare/ecc locations into the buffer for both main and spare ecc, but place newly generated main & spare ecc code of read-data into the buffer for both main and spare ecc. 3) when eagle read nand flash spare area data without ecc --> eagle place the data read from nand flash spare/ecc locations into the buffer for both main and spare ecc. 4) when eagle read nand flash spare area data with ecc --> eagle doesn't place the data read from nand flash spare/ecc locations into the buffer for both main and spare ecc, but place newly generated spare ecc code of read-data into the buffer for spare ecc remaining main ecc as previous data.
s3ci9e0x01 flash interface device samsung electronics 55 10.8. write protection 10.8.1 write protection for bufferram(first 2pages) eagle offers software write protection feature for first 2pages(main + spare area data) of bufferram, which protects bufferram data. this software write protection of bufferram feature is used by setting [1:0]bit value of ?system configuration register(1422h address)?. the default state is locked state; these first 2pages bufferram go to locked state after cold reset or warm reset, and then write is protected. 1 st page bufferram 2 nd page bufferram 3 rd page bufferram 4 th page bufferram 5 th page bufferram 6 th page bufferram 7 th page bufferram 8 th page bufferram unlocked device in cold or warm reset 1) locked system configuration register[1:0] = 00/01/11 initial state system configuration register[1:0] = 10 main area s p are area figure28. write protection available area in bufferram figure29. state diagram of bufferram write protection available on write protection operation not available on write protection o p eration
s3ci9e0x01 flash interface device samsung electronics 56 10.8.2 write protection for nand flash 10.8.2.1 write protection modes eagle offers both hardware and software write protection features for nand flash. the software write protection feature is used by executing the lock block command or lock-tight block command, and the hardware write protection feature is used by executing cold reset or warm reset. 10.8.2.2 write protection commands individual instant secured block protects code and data by allowing any block to be locked or lock-tighten. this write protection scheme offers two levels of protection. the first allows software-only control of write protection(useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed(protects infrequently changed code blocks). the followings summarizes the locking functionality. - all blocks power-up in a locked state. unlock commands can unlock these blocks. - the lock-tight command locks blocks and prevents it from being unlocked. and lock-tight state can be returned to lock state only when cold/warm reset is executed. - writing to unlock start/end address register during locked(or lock-tighten) status doesn?t affect the unlock address , since eagle has another unlock address register internally to prevent this kind of problem. 10.8.2.3 write protection status eagle?s current write protection status can be read in nand flash write protection status register(1450h). there are three bits - us,ls,lts - ,which are not cleared by hot reset. these write protection status registers are updated not as write protection command is entered but as other commands are entered. example1) in default , [2:0] values are 010 -> if host executes unlock block operation, then [2:0] values are still 010 -> if host executes any commands except write protection commands, then [2:0] values turn to 110 -> if host executes lock-tight block operation, then [2:0] values are still 110 -> if host executes any commands except write protection commands, then [2:0] values turn to 101 example2) if host executes lock block operation, then [2:0] values are still previous status -> if host executes any commands except write
s3ci9e0x01 flash interface device samsung electronics 57 protection commands, then [2:0] values turn to 010 -> if host executes lock-tight block operation, then [2:0] values are still 010 -> if host executes any commands except write protection commands, then [2:0] values turn to 001 -> if cold or warm reset is entered, then [2:0] values are 010 figure30. state diagram of nand flash write protection unlock lock- tight nrp pin : high & start block address+ end block address + unlock block command nrp pin : high & lock block command nrp pin : high & lock - tight block command nrp pin : rising edge ( this occurs at cold reset or warm reset ) lock cold or warm reset initial state nrp pin : high & lock - tight block command nrp pin : high & start block address+ end block address + unlock block command
s3ci9e0x01 flash interface device samsung electronics 58 > command sequence : lock block command(02h) > all blocks default to locked after initial cold reset or warm reset > partial block lock is not available ; lock block operation is based on all block unit > unlocked blocks can be locked by using the lock block command and, a lock block?s status can be changed to unlock or lock-tight using the appropriate software commands > command sequence : start block address + end block address + unlock block command(04h) > unlocked blocks can be programmed or erased > an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate software commands > only one sequential area can be released to unlock state from lock state ; unlocking multi area is not available > command sequence : lock-tight block command(01h) > lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. a block that is lock-tighten cannot have it?s state changed by software, only by nrp?s rising edge ; nrp goes low to high during cold/warm reset. ; unlocking multi area is not available > only locked blocks can be lock-tighten by lock-tight command. lock-tighten blocks revert to the locked state at cold/warm reset. locked start block address lock-tighten locked block ( s ) unlocked block ( s ) lock-ti g hten block ( s ) end block address unlocked
s3ci9e0x01 flash interface device samsung electronics 59 note: 1) refer to ?status register(1440h)? figure32. flowchart of nand flash write protection figure31. operations of nand flash write protection u u n n l l o o c c k k b b l l o o c c k k s s t t a a t t e e l l o o c c k k b b l l o o c c k k s s t t a a t t e e l l o o c c k k - - t t i i g g h h t t b b l l o o c c k k s s t t a a t t e e write ?start block address? to address write ?end block address? to address register write ?unlock block command(04h)? state change? write ?lock-tight block command(01h)? write ?lock block command(02h)? start (after warm or cold reset) end yes no state change? yes no state change? yes no change to lock-tighten state? yes no
s3ci9e0x01 flash interface device samsung electronics 60 10.8.2.4 write protection truth table l lt or lt & ul 1) l or l & ul l current status current status l (all blocks) ul l & ul current status l & ul lt lt (all blocks) current status lt & ul l & ul l & ul current status l & ul l & lt lt (all blocks) current status lt (all blocks) lt & ul 2) lt & ul current status lt & ul 1) l & ul & lt ul & lt current status lt & ul note: 1) for example, ?lt or lt&ul? status means ? lt(all blocks) status? or ?lt(some area) and ul(the other area). 2) for example, it means that lt and ul commands are consecutively entered regardless of order. next status command l : locked status, ul : unlocked status, lt : lock-tighten status current status next cmd (e.g unlock) any command except write protection command nand flash write protection command register ( 144ah register) current status (e.g lock) nand flash write protection status register ( 1450h register) next status (e.g unlock) 1450h register(=eagle?s status) is updated by the next command except write protection command . " " " " write protection guidance 1450h register(=eagle?s status) is not updated at this moment .
s3ci9e0x01 flash interface device samsung electronics 61 11. technical note 11.1. ring oscillator this device has internal ring oscillator for being used as internal clock and for generation of nand flash control signal. 11.2. voltage level detector (por = power on reset) this device has internal voltage level detector for initiating cold reset automatically. 0v 1.8v cmd int oscillator is active bootload operation starts 200us later than por level detection. bootload o p eration
s3ci9e0x01 flash interface device samsung electronics 62 11.3. nand flash type detection algorithm this algorithm is for detecting nand flash type. ce2ena is the bit 11 of system configuration register , which specifies nand flash type whether 512mb single or 512mb ddp. host reads nand flash id start ce2ena = 0 (default) : 512mb single ce2ena = 1 : 512mb ddp is the device code 256mb ? host sets ?ce2ena? to 1 host sets the bit 11 of ?block address register? to 1 1) host reads nand flash id is it all ffh ? ye s ye s no is the device code 512mb ? ye s no fail no is the device code 256mb ? ye s no note : 1) the bit 11 data of ?block address register? determines whether to access fnce2 or not, for it is a divide factor of 256mb/512mb. host needs not to set ?ce2ena? a g ain . host needs not to set ?ce2ena? a g ain . nand flash is 256mb sin g le nand flash is 512mb sin g le nand flash is 512mb ddp (but, this is not considered device)
s3ci9e0x01 flash interface device samsung electronics 63 11.4. internal register reset case internal register default value cold reset warm reset hot reset nand reset 1400h controller information 1002h x x x x 1402h block address 0000h o o o x 1404h page address & page count 0000h o o o x 1406h start buffer 0000h o o o x 1420h command 0000h o o o x 1422h system configuration 7051h o ! 1) ! 2) x 1440h controller status 0000h o o o x 1422h interrupt 8000h ! 3) o o x 1446h ecc result of main 0000h o o o x 1448h ecc result of spare 0000h o o o x 144ah nand write protection command 0002h o o x x 144ch unlock start block address 0000h o o x x 144eh unlock end block address 0000h o o x x 1450h nand write protection status 0002h o o x x o : go to default value, x : not change note : 1) ce2ena bit of system configuration register are not initialized at warm reset. 2) ce2ena and bss bits of system configuration register are not initialized at hot reset. 3) interrupt register goes to 8080h at cold reset.
s3ci9e0x01 flash interface device samsung electronics 64 11.5. pin connection guidance between host and eagle # # # # navd connected case # # # # navd disconnected case nce add<0> navd nce navd add<1> add<2> add<12 add<0> add<1> add<2> add<11 add<3> gnd or vdd host ea g le nce add<0> navd nce add<1> add<2> add<12 add<0> add<1> add<2> add<11 add<3> gnd or vdd host ea g le > if host uses byte-order typed address, add<0> can be used as byte/word selection pin. > if host uses byte-order typed address, add<0> can be used as byte/word selection pin. >in navd disconnected case, navd can be tied to nce or gnd. gnd
s3ci9e0x01 flash interface device samsung electronics 65 11.6. asynchronous page read guidance address cl k navd nce address noe inv a li d data n data n+1 data n+1 n+2 n+3 n + 4 n+2 data n+3 data dq t apa tce toe n+4 data invalid add r ess taes : taes should not be ove r address example 1 (o.k) n x?.xxx00 bit n+1 x?.xxx01 bit n+2 x?.xxx10 bit n+3 x?.xxx11 bit example 2 (o.k) x?.xxx10 bit x?.xxx11 bit x?.xxx00 bit x?.xxx10 bit example3 (not o.k) x?.xxx11 bit x?.xxx11 bit x?.xxx01 bit x?.xxx10 bit n+4 x?.xxx01 bit x?.xxx10 bit x?.xxx10 bit there is no problem for there is a change of one of add<0:1> n+1 address is ignored for there is no chan g e of add<0:1>. > eagle?s internal address detector latches add<0:11> whenever one of add<0:1> changes. > there is no problem while host sequentially reads data with changing one of add<0:1> and fixing nce & noe to low.
s3ci9e0x01 flash interface device samsung electronics 66 12. electrical specifications 12-1. absolute maximum ratings parameter symbol rating unit vcc v cc 3.6 voltage on any pin relative to vss all other pins v in 3.6 v latch-up current i latch 200 ma storage temperature t stg -65 to 150 o c note: permanent device damage may occur if absolute maximum ratings are exceeded. exposure to absolute maximum rating conditions for extended periods may affect reliability. 12-2. recommended operating ratings 12-2-1. supply voltage(voltage reference to gnd) 1.8v part 2.5v part parameter symbol min typ. max min typ. max unit v cc 1.65 1.8 1.95 2.3 2.5 2.7 supply voltage v ss 0 0 0 0 0 0 v 12-2-2. temperature parameter symbol rating unit commercial temperature t a (commercial temp.) 0 to 70 industrial temperature t a (industrial temp.) -25 to 85 o c
s3ci9e0x01 flash interface device samsung electronics 67 12-3. dc characteristics 1.8v part 2.5v part parameter symbol test condition min typ max min typ max unit input leakage current i li v in = v ss to v cc v cc = v cc(max) -7 - 7 -10 - 10 output leakage current i lo v out = v ss to v cc v cc = v cc(max) -7 - 7 -10 - 10 standby current i ccs v cc = v cc(max) nce = nrp = v ih int = floating - 25 40 30 60 ua active async. read current i ccr1 v in = v ih or v il nce = v il noe = v ih - 15 20 20 30 active sync. read current i ccr2 nce = v il noe = v ih continuous burst clk = 45mhz - 15 20 20 30 active program current i ccw program in progress - 15 20 20 30 active erase current i cce erase in progress - 15 20 20 30 ma input high voltage v ih - vcc- 0.4 - vcc+ 0.4 1.7 - - input low voltage v il - -0.5 - 0.4 - - 0.7 high level output voltage v oh i oh = -100ua vcc=vcc(min) vcc- 0.2 - - 1.9 - - low level output voltage v ol i ol = 100ua vcc=vcc(min) - - 0.2 - - 0.5 v input capacitance 1) c in any input and bi -directional buffer s - - 10 - - 10 output capacitance 1) c out any output buffers - - 10 - - 10 pf note : 1. this value excludes package parasitic
s3ci9e0x01 flash interface device samsung electronics 68 12-4. ac test condition parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc / 2 output load c l = 30pf 0v vcc vcc / 2 vcc / 2 input & output te s t p i n t in p ut pulse and test point device under test cl = 30pf out p ut load
s3ci9e0x01 flash interface device samsung electronics 69 12-5. ac characteristics ! asynchronous read ac parameters parameter description min typ max unit tce access time from nce low - - 55 ns toe output enable to output valid - - 23 ns tacc asynchronous access time - - 55 ns tae random access navd-data valid - - 55 ns toh output hold from nce or noe change, whichever occurs first 0 - - ns tapa page address access time - - 40 ns tasa address setup to navd high 7 - - ns taes nce & navd setup to valid address - - 10 ns tca nce setup to navd falling edge 0 - - ns ! synchronous read ac parameters parameter description min typ max unit tces nce setup time to clk 5 - - ns tiacc initial access time @ 40mhz - - 94 ns tbacc burst access time valid clock to output delay - - 19 ns tbdh data hold time from next clock cycle 4 - - ns tavds navd setup time to clk 5 - - ns tavdh navd hold time to clk 7 - - ns tacs address setup time to clk 5 - - ns tach address hold time to clk 7 - - ns toh output hold from nce or noe change, whichever occurs first 0 - - ns toe output enable to output valid - - 23 ns toes noe setup to clk 2 x tclk 1) - - ns tclkh flsclk high time 10 - - ns tclkl flsclk low time 10 - - ns tca nce setup to navd falling edge 0 - - ns
s3ci9e0x01 flash interface device samsung electronics 70 note : 1) tclk = tclkh + tclkl ! write ac parameters parameter description min typ max unit tavdp navd low time 12 - - ns taavds asynchronous address setup time 7 - - ns taavdh asynchronous address hold time 7 - - ns tds data setup time 5 - - ns tdh data hold time 4 - - ns twc write cycle time 30 - - ns twpl write pulse width low 10 - - ns twph write pulse width high 20 - - ns tcs nce setup time 0 - - ns tch nce hold time 4 - - ns tawes address setup to nwe low 5 - - ns tvlwh navd rising edge to nwe rising edge 10 - - ns
s3ci9e0x01 flash interface device samsung electronics 71 13. package dimension #a1 d e a a2 #a1 index mark (optional) f1 f2 e b
s3ci9e0x01 flash interface device samsung electronics 72 description symbol unit : mm min. nom. max. package height a ball height a2 ball diameter b package body width d package body length e ball pitch e ball center to edge f1/f2 1.0 1.1 1.2 0.15 0.2 0.25 0.25 0.3 0.35 5.9 6 6.1 5.9 6 6.1 - 0.5 - - 0.75/0.75 -
s3ci9e0x01 flash interface device samsung electronics 73 1. synchronous read fail in last word of bufferram description) reading last page(8 th ) last word(264 th ) of bufferram with synchronous read timing is not allowed in specification. (refer to figure1) short-term workaround) since current ?nand flash media driver? never accesses this word, this error will not affect host?s operation anymore. main area s p are area 1 st page bufferram 2 nd page bufferram 3 rd page bufferram 4 th page bufferram 5 th page bufferram 6 th page bufferram 7 th page bufferram 8 th page bufferram reading this word with synchronous read timing is not allowed. since current ?nand flash media driver? never accesses this word, this error will not affect host?s o p eration an y more. < synchronous read fail in bufferram > errata
s3ci9e0x01 flash interface device samsung electronics 74 2. ecc fail 2-1. ecc fail at reading data of all erased page description) when data of erased page is read, the ecc result is always reported as ecc fail. short-term workaround) addition of detection algorithm of erased page in software is required. the algorithm is to check whether lsn & eccs(ecc code of lsn) are all ffh or not. if lsn & eccs are all ffh, it means that the page is erased one, then s/w can ignore this ecc fail. is ecc result fail ? are lsn & eccs all ffh ? no ye s previous step continue next step no it is real ecc fail, continue next step. ye s ignore this ecc fail , the page is erased one. additional detection algorithm < additional detection algorithm for software walk-around > lsn main area data wc bi reserved eccm eccs < the page assignment of nand flash > spare area data
s3ci9e0x01 flash interface device samsung electronics 75 2-2. ecc fail at programming spare area data alone description) while only spare area is programmed, eccm(ecc code of main area) is reset to 00h. short-term workaround)] avoid partially programming lsn data. the suggested procedure of spare area program is ; program main area data + lsn data at a time, and then program wc without ecc. lsn main area data wc bi reserved eccm eccs < the page assignment of nand flash > spare area data < suggested program guideline for walk-around > bi lsn bi erased(reserved) eccm eccs erased main area data erased page lsn bi eccm eccs main area data step 1 : program ?main area data + lsn ? with ecc erased erased erased erased erased erased(reserved) erased step 2 : program ?wc ? without ecc
s3ci9e0x01 flash interface device samsung electronics 76 3. sequential reset fail description) sequential reset inputs are prohibited no matter what combination is between warm reset/ hot reset/nand flash reset is. cold reset isn?t concerned with this fail. for example, 1) warm reset ? hot reset 2) warm reset ? warm reset 3) hot reset ? warm reset 4) hot reset ? hot reset 5) hot reset ? nand flash reset 6) etc. short-term workaround) if you can?t avoid sequential resets case in application, the suggested walk-around is like the following. reset reset nand another operation between resets can break through this failure.

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